1. Field of the Invention
The present invention relates to programmable logic devices. More particularly, the present invention relates to a programmable logic device having ferroelectric memory cells as a non-volatile configuration memory to store the definitions of logic functions.
2. Description of the Related Art
Programmable logic devices are a class of integrated circuits that offer a vast array of configurable building blocks including logic gates for users to implement an application-specific function. Their fundamental elements include: logic blocks containing basic logic gates (which are sometimes implemented with look-up tables) and flip-flops, multiplexers, programmable interconnections for wiring between internal elements, and programmable input/output (I/O) blocks for implementing various I/O port configurations. They further have a configuration memory to store the definition of logical block functions, programmable interconnections, and programmable I/O block configurations. Such information is called “configuration data.”
Programmable logic devices are generally categorized into three groups as follows. Devices in the first category have programmable logic blocks, interconnections, and I/O blocks, and their configuration memories are volatile; i.e., their data is lost upon power shutdown. Devices in the second category are similar to the first category in terms of functional structure, but their configuration data is non-volatile. In the third category, their logic blocks are designed on the basis of programmable logic array architectures, with non-volatile configuration storage.
As a specific example of the first category, the U.S. Pat. No. 4,642,487 discloses a programmable logic device employing a static random access memory (SRAM) to store its configuration data. Since the SRAM cells used in this device are volatile, the configuration data on the chip disappears when the power is removed. Additional non-volatile memories, such as programmable read-only memory (PROM) and erasable PROM (EPROM), are therefore necessary to store the configuration data for this type of device. When the device is powered up again, its configuration data should be restored from an external memory device to internal SRAM cells. The use of such an off-chip non-volatile memory raises the cost of products, besides consuming precious board space.
The above shortcomings of the first-category devices are solved in the second category of programmable logic devices which integrate non-voltage configuration data storage. In the second category, each device contains configuration data in its integral ferroelectric memory or magnetic random-access memory (MRAM), which are both non-volatile. One specific example is shown in the Japanese Patent No. 3121862, which proposes a programmable logic device with ferroelectric memories. Ferroelectric memory is particularly suitable for programmable logic device applications because of its advantage in operation speed. Other types of non-volatile memories such as PROM, EPROM, electrically erasable PROM (EEPROM), or flash memory are not used in the second category, since they require the integration of high-voltage transistors and their speed is insufficient to meet the needs of programmable logic devices.
Programmable logic devices that belong to the third category use EPROM, EEPROM, or flash memory as non-volatile configuration data storage, as in the second category. They are also called “Complex Programmable Logic Devices” (CPLD), as distinguished from the second category, which Stephen D. Brown et al. elaborate in their publication entitled “Field Programmable Gate Arrays” (Kluwar Academic Publishers).
The present invention aims at the programmable logic devices that belong to the first and second categories described above, which are collectively called “Field Programmable Gate Array” (FPGA). Conventional FPGAs, however, have some problems, one of which is a limitation in the number of logic gates per unit chip area. To cover this deficiency, researchers have studied such devices that can store multiple sets of configuration data. As distinguished from FPGA, this architecture is called “Dynamically Programmable Gate Array” (DPGA). For more details, refer to A. DeHon, “Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density,” Fourth Canadian Workshop of Field-Programmable Devices, 1996.
The DPGAs mentioned above are a member of the first category of programmable logic devices since their configuration data is stored in a dynamic RAM (DRAM) which is volatile. With the DPGA architecture, we can virtually increase the number of logic gates implemented on a single device. One problem is, however, that the above publication tells us little about how to switch the configuration data. Another problem is, of course, that their configuration memory is volatile. This means that an external non-volatile memory is necessary, which makes the board design more difficult since it increases the component count, costs, and board space consumption. Yet another difficulty about DPGA is that no specific method of configuration switching is disclosed.
As a general problem with programmable logic devices, it is known that some improper internal connections could happen on power-up in the case the configuration memory has not been loaded with data. If two driver outputs in opposite logic states are wired together, the conflict could produce an undefined voltage level, resulting in a large current flow within a device. A possible countermeasure is to disable the output drivers of logic blocks each time the device is powered up, until the configuration data becomes ready (P. Chow et al., IEEE Transaction on Very Large Scale Integration Systems, vol.7, No.3, pp. 321-330, September 1999). This method of disabling output drivers has a side effect that a device cannot start operation immediately after power-up.
Also, in conventional programmable logic devices, loading of their configuration data often takes a long time to complete. The users wish for an improved data loading mechanism for this reason.
Configuration data of programmable logic devices is an asset of the company that developed it. Conventional devices, however, provide little security measures to protect such assets from stealing, tampering, or other unauthorized access. It is therefore desired to introduce a data protection mechanism into programmable logic devices.
The Japanese Patent No. 3,121,862 discloses a programmable logic device using ferroelectric random access memories. This programmable logic device, however, may fail to recall data out of ferroelectric memories in power-up, or may fail to store data in ferroelectric memories in power-down. T. Tamura et al. wrote a report that reveals some dynamic behaviors of ferroelectric capacitors (T. Tamura et al., ISIF Digest, p.1.2.2, 2001). That nature of capacitors could lead to a problem in recovering data from the polarization state of each ferroelectric capacitor, as a consequence of application of a rapidly rising voltage at the time of power-up. That is, configuration data stored in a ferroelectric memory could be destroyed on power-up, although it has to be non-volatile.
Also, to ensure the reliable retention of stored data, it is considered desirable to fully apply a supply voltage to ferroelectric SRAM cells before removing power from them. It is known, however, that a ferroelectric capacitor has a tendency to prefer one state over the other if a full supply voltage is applied to it for a long period of time. This “imprint” effect, a phenomenon due to a shift of the hysteresis loop, makes it difficult to write data to ferroelectric memory cells.